As is known, and as illustrated schematically in FIG. 1, a non-volatile memory device 1, for example of a flash type, comprises a memory array 2 having array memory cells 3 arranged in rows and columns. In particular, each array memory cell 3 comprises a floating-gate transistor, and storage of a logic state is performed by programming the corresponding threshold voltage through injection of a quantity of electrical charge in its floating-gate region. In the memory array 2, wordlines (WLs) connect gate terminals of cells set on a same row, and bitlines (BLs) connect drain terminals of cells set on a same column. Individual rows of the memory array are addressed by means of a row decoder 4, which receives at its input an encoded address and biases the wordline of the row each time addressed at a stable and precise voltage, the value of which depends on the type of operation that it is desired to be performed from among reading, verify and modify (programming or erasure).
Individual columns of the memory array are addressed by means of a column decoder 5, which also receives at its input the aforesaid encoded address and biases the bitline of the column each time addressed at a voltage such as to guarantee the presence on the drain terminal of the memory cell of a pre-set electrical potential, which is also stable and controlled. A biasing circuit 6 is connected to the row and column decoders 4, 5, receives a supply voltage VDD, and generates the biasing voltages required for the wordlines WL and the bitlines BL, during the various operating steps of the non-volatile memory device 1. According to the information stored, the array memory cells 3 are distinguished into: erased cells (logic state stored “1”), in the floating-gate region of which no electrical charge is stored; and written or programmed cells (logic state stored “0”), in the floating-gate region of which an electrical charge is stored sufficient to determine a sensible increase in the corresponding threshold voltage. Alternatively, information in the memory cells can be stored with a larger number of bits, to each combination of bits corresponding to a different level of charge stored and a different threshold voltage (so-called “multilevel storage”).
Operation of the non-volatile memory device 1 often requires the determination of the content of an array memory cell 3, in particular during operations of reading of the memory content, and of verification of this content after previous modify operations.
The method most widely used for reading the content of an array memory cell 3 envisages the comparison of an electrical quantity correlated to the current flowing through the cell with an analogous electrical quantity correlated to a reference current having a known value. Typically, the reference current flows through a reference memory cell 7, of known content. In a way not illustrated, a plurality of reference memory cells is provided in a non-volatile memory device, each of which is used during reading of a given portion of the memory array. Furthermore, each reference usually is not made by a single cell, but rather by a bank of reference memory cells arranged in rows and columns, in which just one of the cells effectively acts as reference element during reading The other cells surrounding it have the sole purpose of reproducing the same environment that surrounds the array memory cell the content of which is to be read, so that its physical structure becomes as similar as possible to that of the memory cell, thus reducing behavioral differences due, for example, to lithographic aspects of the process. The reference memory cell advantageously experiences the same changes with temperature and/or supply voltage as those experienced by the array memory cells (so that these variations will not lead to reading errors). Moreover, during a single operating step of the memory, a number of reference memory cells, having different current reference values, can be used.
The non-volatile memory device 1 consequently comprises a reading circuit 8, generally known as “sense amplifier”, which is connected to the bitlines BL, BLref, respectively, of the array memory cells 3 and of the reference memory cells 7, and carries out the aforesaid comparison for recognizing the data stored in the memory. In particular, to perform reading of an array memory cell 3, a reading voltage is supplied to its floating-gate terminal, by means of the corresponding wordline WL, the reading voltage having a value comprised between the threshold voltage of an erased memory cell and that of a written memory cell. If the memory cell is written, the reading voltage is lower than its threshold voltage, and hence no appreciable current flows. Instead, if the memory cell is erased, the reading voltage is higher than its threshold voltage, and hence an appreciable current flows in the memory cell. This current is then compared with the reference current that flows in the reference memory cell 7, which is appropriately biased by means of the respective reference wordline WLref.
A common drawback in memory devices of the type described above is represented by the fact that biasing of a memory cell for determining its content induces in the cell an electrical stress, which, as time passes, can alter its performance. This problem is aggravated by the continuous technological scaling of electronic devices, which leads to the manufacturing of components with increasingly thinner oxide regions. In particular, repeated accesses to the reference memory cells can lead to considerable shifts of the corresponding threshold voltages, with obvious consequences on the reliability of the reading operations, and/or reduction of their life with possible premature breakage.
This problem is particularly felt in the case of the memory cells used as reference, which, during each reading or modify operation, can be addressed a very high number of times. For example, in a memory sector made up of 2048 columns and 256 rows, with read parallelism (“paral”) equal to 64, during a verify operation after erasing (in which, as is known, reference memory cells are selected for verifying correct erasing of array memory cells), a reference memory cell is subjected to a number of accesses N(sector) equal to:N(sector)=(Ncol*Nrow)/paral=(2048*256)/64=8192
Considering a memory partition of 4 Mb, the number of accesses N(partition) is equal to:N(partition)=N(sector)*num_sectors=8192*8=65536whilst considering a 64-Mb memory, the number of accesses N(array) is equal to:N(array)=N(partition)*num_partitions=65536*16=108576
Given that, with technological progress, electronic consumer devices require an increasingly high amount of memory, the number of accesses to which the reference cells are subjected is bound to further increase.
In addition, size reduction of memory cells also leads to an aggravation of problems linked to charge retention within oxide layers and, in particular, of the phenomenon of random shift of the threshold voltage or Random Threshold Shift (“RTS”). For example, tests performed by the present applicant have demonstrated instability of the reference threshold in the memory cells of up to 300 mV. Such a variability can clearly lead to errors in the determination of the stored information.
On account of the aforesaid problems, it has consequently become necessary to revise the methodology of use of memory cells as stable and durable current references.
There has, for example, been proposed the use of reference-current generators instead of reference memory cells. This solution does not, however, enable the natural variations of the array memory cells with temperature and/or supply voltage to be followed.
For the above reason, the use of a reference-current generator has been proposed, that is able to adapt to variations of temperature and supply voltage in so far as it comprises a resistive element that is variable as a function of these parameters. However, the resistive component, by its very nature, does not have a characteristic of variability identical to that of an array memory cell, making the proposed circuit difficult to implement.
In another approach, a reading circuit for a non-volatile memory device has been proposed, provided with a sample-and-hold stage, in particular comprising a storage capacitor, for detecting and maintaining a sample of a reference voltage correlated to the reference current flowing in a reference memory cell. Accordingly, access to the reference memory cell is limited to just the time necessary for the capacitor to charge to the reference voltage, after which the cell is deselected, and reading operations proceed using the reference voltage held by the capacitor. A solution of this sort, although advantageous in so far as it limits access to the reference memory cells and the consequent electrical stress, is not, however, free from problems. In particular, the voltage maintained by the storage capacitor is subject to a natural reduction over time, on account of the capacitor discharge through leakage current, so that the reference voltage is not perfectly stable Also, it is necessary to refresh periodically the charge stored in the capacitor, by accessing again the reference memory cell. Each refresh operation, in addition to causing an electrical stress in the reference cell, is exposed to the problem of random threshold shift (RTS) of the cell, thus further contributing to the non-perfect stability of the reference voltage.